In third generation (3G) cellular systems for Frequency Division Duplex (FDD) and Time Division Duplex (TDD), there are retransmission mechanisms in the Acknowledgement Mode of the Radio Link Control (RLC) layer to achieve high reliability of end-to-end data transmissions. The RLC layer is a peer entity in both the Radio Network Controller (RNC) and the User Equipment (UE).
A block diagram of a UMTS Terrestrial Radio Access Network (UTRAN) MAC-hs layer architecture is illustrated in FIG. 1, and a block diagram of the user equipment (UE) MAC-hs architecture is shown in FIG. 2. The architecture shown in FIGS. 1 and 2 is described in detail co-pending U.S. patent application Ser. No. 10/270,822 filed on Oct. 15, 2002 which is assigned to the present assignee. The UTRAN MAC-hs 30 shown in FIG. 1 comprises a transport format resource indicator (TFRI) selector 31, a scheduling and prioritization entity 32, a plurality of Hybrid Automatic Repeat (H-ARQ) processors 33a, 33b, a flow controller 34 and a priority class and transmission sequence number (TSN) setting entity 35.
The UE MAC-hs 40 comprises an H-ARQ processor 41. As will be explained with reference to both FIGS. 1 and 2, the H-ARQ processors 33a, 33b in the UTRAN MAC-hs 30 and the H-ARQ processor 41 in the UE MAC-hs 40 work together to process blocks of data.
The H-ARQ processors 33a, 33b in the UTRAN MAC-hs 30 handle all of the tasks that are required for the H-ARQ process to generate transmissions and retransmissions for any transmission that is in error. The H-ARQ processor 41 in the UE MAC-hs 40 is responsible for generating an acknowledgement (ACK) to indicate a successful transmission, and for generating a negative acknowledgement (NACK) to indicate a failed transmission. The H-ARQ processors 33a, 33b and 41 process sequential data streams for each user data flow.
As will be described in further detail hereinafter, blocks of data received on each user data flow are assigned to H-ARQ processors 33a, 33b. Each H-ARQ processor 33a, 33b initiates a transmission, and in the case of an error, the H-ARQ processor 41 requests a retransmission. On subsequent transmissions, the modulation and coding rate may be changed in order to ensure a successful transmission. The data block to be retransmitted and any new transmissions to the UE are provided by the scheduling and prioritization entity 32 to the H-ARQ entities 33a, 33b. 
The scheduling and prioritization entity 32 functions as radio resource manager and determines transmission latency in order to support the required QoS. Based on the outputs of the H-ARQ processors 33a, 33b and the priority of a new data block being transmitted, the scheduling and prioritization entity 32 forwards the data block to the TFRI selector 31.
The TFRI selector 31, coupled to the scheduling and prioritization entity 32, receives the data block to be transmitted and selects an appropriate dynamic transport format for the data block to be transmitted. With respect to H-ARQ transmissions and retransmissions, the TFRI selector 31 determines modulation and coding.
It is highly desirable for the retransmitted data blocks to arrive at the RLC entity of the receiving side (i.e., the UE) as soon as possible for several reasons. First, the missed data block will prevent subsequent data blocks from being forwarded to higher layers, due to the requirement of in-sequence delivery. Second, the buffer of the UE needs to be sized large enough to accommodate the latency of retransmissions while still maintaining effective data rates. The longer the latency is, the larger the UE buffer size has to be to allow for the UE to buffer both the data blocks that are held up and continuous data receptions until the correct sequence data block is forwarded to higher layers. The larger buffer size results in increased hardware costs for UEs. This is very undesirable.
Referring to FIG. 3, a simplified flow diagram of the data flow between a Node B (shown at the bottom of FIG. 3) and a UE (shown at the top of FIG. 3) is shown. PDUs from higher level processing are scheduled and may be multiplexed into one data block. A data block can only contain PDUs of higher layers of the same priority. A unique TSN is assigned to each data block by the scheduler. The higher layers may provide a plurality of streams of different priorities of PDUs, each priority having a sequence of TSNs. The scheduler then dispatches the data blocks to the plurality of H-ARQ processors P1B-P5B. Each H-ARQ processor P1B-P5B is responsible for processing a single data block at a time. For example, as shown in FIG. 3, the Priority 1 PDUs comprise a sequence illustrated as B11-B1N. Likewise, the Priority 2 PDUs are sequenced from B21-B2N and the Priority 3 PDUs are sequenced from B31-B3N. These PDUs are scheduled (and may be multiplexed) and affixed a TSN by the common scheduler. For purposes of describing the invention, it is assumed that one PDU equals one data block. After a data block is scheduled to be processed by a particular processor P1B-P5B, each data block is associated with a processor identifier, which identifies the processor P1B-P5B that processes the data block.
The data blocks are then input into the scheduled Node B H-ARQ processors P1B-P5B which receive and process each data block. Each Node B H-ARQ processor P1B-P5B corresponds to an H-ARQ processor P1UE-P5UE within the UE. Accordingly, the first H-ARQ processor P1B in the Node B communicates with the first H-ARQ processor P1UE in the UE. Likewise, the second H-ARQ processor P2B in the Node B communicates with the second H-ARQ processor P2UE in the UE, and so on for the remaining H-ARQ processors P3B-P5B in the Node B and their counterpart H-ARQ processors P3UE-P5UE respectively within the UE. The H-ARQ processes are timely multiplexed onto the air interface and there is only one transmission of an H-ARQ on the air interface at one time.
For example, taking the first pair of communicating H-ARQ processors P1B and P1UE, the H-ARQ processor P1B processes a data block, for example B11, and forwards it for multiplexing and transmitting it over the air interface. When this data block B11 is received by the first H-ARQ processor P1UE, the processor P1UE determines whether or not it was received without error. If the data block B11 was received without error, the first H-ARQ processor P1UE transmits an ACK to indicate to the transmitting H-ARQ processor P1B that it has been successfully received. On the contrary, if there is an error in the received data block B11, the receiving H-ARQ processor P1UE transmits a NACK to the transmitting H-ARQ processor P1B. This process continues until the transmitting processor P1B receives an ACK for the data block B11. Once an ACK is received, that processor P1B is “released” for processing another data block. The scheduler will assign the processor P1B another data block if available, and can choose to retransmit or start a new transmission at any time.
Once the receiving H-ARQ processors P1UE-P5UE process each data block, they are forwarded to the reordering buffers R1, R2, R3 based on their priority; one reordering buffer for each priority level of data. For example, Priority 1 data blocks B11-B1N will be received and reordered in the Priority 1 reordering buffer R1; Priority 2 data blocks B21-B2N will be received and reordered in the Priority 2 reordering buffer R2; and the Priority 3 data blocks B31-B3N will be received and reordered by the Priority 3 reordering buffer R3.
Due to the pre-processing of the data blocks by the receiving H-ARQ processors P1UE-P5UE and the ACK/NACK acknowledgement procedure, the data blocks are often received in an order that is not sequential with respect to their TSNs. The reordering buffers R1-R3 receive the out-of-sequence data blocks and attempt to reorder the data blocks in a sequential manner prior to forwarding onto the RLC layer. For example, the Priority 1 reordering buffer R1 receives and reorders the first four Priority 1 data blocks B11-B14. As the data blocks are received and reordered, they will be passed to the RLC layer.
On the receiving side, the UE MAC-hs, (which has been graphically illustrated as MAC-hs control), reads the H-ARQ processor ID, whether it is sent on a control channel such as the HS-SCCH or whether the data block has been tagged, to determine which H-ARQ processor P1UE-P5UE has been used. If the UE receives another data block to be processed by the same H-ARQ processor P1UE-P5UE, the UE knows that that particular H-ARQ processor P1UE-P5UE has been released regardless of whether or not the previous data block processed by that H-ARQ processor P1UE-P5UE has been successfully received or not.
FIG. 4 is an example of a prior art system including an RNC, a Node B, a UE and their associated buffers. This example assumes that the UE is the receiving entity and the Node B is the transmitting entity. In this prior art system, a PDU with SN=3 is not received successfully by the UE. Therefore, the RLC in the UE requests its peer RLC layer in the RNC for a retransmission. Meanwhile, the PDUs with SNs=6-9 are buffered in the Node B, and PDUs with SNs=4 and 5 are buffered in the UE. It should be noted that although FIG. 4 shows only several PDUs being buffered, in reality many more PDUs (such as 100 or more) and PDUs from other RLC entities may be buffered.
As shown in FIG. 5, if a retransmission of the PDU with SN=3 is required, it must wait at the end of the queue in the Node B buffer, and will be transmitted only after the PDUs with SNs=6-9 are transmitted. The PDUs in the UE cannot be forwarded to the upper layers until all PDUs are received in sequence.
In this case, the PDU with SN=3 stalls the forwarding of subsequent PDUs to higher layers, (i.e. SNs=4-9), assuming all the PDUs are transmitted successfully. Again, it should be noted that this example only reflects 11 PDUs, whereas in normal operation hundreds of PDUs maybe scheduled in advance of retransmitted data PDUs, which further aggravates transmission latency and data buffering issues.
It would be desirable to have a system and method whereby the retransmitted data can avoid the delays due to congestion in the transmission buffers.